A scan path test is available as a technique (DFT) for facilitating detection of faults in a semiconductor integrated circuit. In a case where operating frequencies differ for respective ones of a plurality of clock domains that exist in user mode, there are instances where a speed test is conducted for each individual clock domain. In order to perform fault analysis when a failure occurs in a specific clock domain, a scan path test is conducted for each individual clock domain. Here “user mode” is an operational mode and is used to distinguish it from the scan path test mode that is set when a scan path test is executed. It signifies an operational mode in which the internal functions of a semiconductor integrated circuit operate as usual at times other than when the scan path test mode is in effect. Although it can also be referred to as “normal mode”, the term “user mode” will be employed in the description that follows. Further, an operational clock supplied at the time of operation in the user mode will be referred to as a “user clock” in order to distinguish it from a test clock supplied at the time of the scan path test, and a terminal at which the user clock is supplied will be referred to as a “user clock terminal”.
In a large-scale semiconductor integrated circuit having a large number of terminals, use is made of a scan path test that involves providing test clock terminals the number of which is the same as or approximately the same as the number of individual clock domain in user mode, and controlling each of the clock domains individually.
On the other hand, in the case of a small-scale semiconductor integrated circuit with a small number of terminals or a semiconductor integrated circuit the number of test terminals of which is limited for the purpose of multiple parallel testing, a test structure that employs fewer test clock terminals is sought. There is also a need to avoid, to the extent possible, an increase in additional circuits for testing.
Patent Document 1 discloses a method of testing a circuit, which has two or more clock domains, at respective domain test clock rates and under the control of a main test clock. FIG. 1 illustrates the arrangement disclosed in Patent Document 1. This circuit has core logic 26 and a plurality of scannable memory elements each having a clock input, an input connected to an output of the core logic 26 and/or an output connected to an input to the core logic 26. The dashed line represents the boundary between two clock domains. The circuit is configurable in the scan path test mode in which memory elements 20, 22, 28, 30 are connected to define one or more scan chains in each domain, and in the user mode in which the memory elements are connected to the core logic in normal operational mode. The method comprises configuring the memory elements in the scan path test mode and simultaneously clocking a test signal into each scan chain of each clock domain. With regard to each clock domain having a domain test clock signal synchronous with respect to the main test clock signal, clocking includes clocking the test signal at a shift clock rate derived from the main test clock signal and, with regard to each clock domain having a domain test clock signal which is asynchronous with respect to the main test clock signal, clocking all but a predetermined number of bits of the test signal at a first domain shift clock rate derived from the main test clock signal followed by clocking the predetermined number of bits of the test signal at a second domain shift clock rate corresponding to the domain test clock rate. The method further includes configuring the memory elements of each scan chain in the user mode in which the memory elements of each scan chain are interconnected by the core logic in the normal operational mode; clocking each memory element in each scan chain at its respective domain test clock rate for at least one clock cycle; configuring the memory elements in the scan path test mode; and clocking a test response pattern out of each of the scan chains at its respective domain shift clock rate during a respective scan-out interval. All respective scan-out intervals overlap in time for a plurality of clock cycles at the highest of the respective clock rates.
Further, Patent Document 2 discloses a scan chain connecting method (see FIG. 2) for preventing wiring congestion when all scan chains are configured by connecting groups in a semiconductor integrated circuit in which a plurality of scan chain groups have been configured. Shown in FIG. 2 are an input/output cell area 101, scan chain groups 102 to 110, a scan input cell 111, a scan output cell 112 and centroids 113 to 121 of respective scan chain groups. In this scan chain connecting method of configuring all scan chains by connecting scan chain groups after scan chains have been connected in individual scan chain groups, the sequence in which scan chain groups are connected together is decided based upon a prescribed evaluation relating to layout position information of cells concerning the respective clock systems of the scan chain groups. In accordance with this method, it is possible to decide a sequence for connecting scan chain groups together, so as to shorten the connection wiring between scan chains, based upon a prescribed evaluation of layout position information of cells concerning the clock systems within the scan chain groups. This makes it possible to prevent wiring congestion when configuring scan chains in the overall semiconductor integrated circuit. On the basis of the prescribed evaluation, the sequence for connecting scan chain groups is in order of decreasing mutual distance between centroid coordinates of all flip-flop layout positions included in respective scan chain groups; in order of decreasing mutual distance between coordinate positions of gated cells present in a clock group system of a scan chain; or in order of decreasing mutual distance between coordinate positions of any pre-designated marked cells in a clock system of a scan chain group. Alternatively, on the basis of the prescribed evaluation, sets of flip-flops having the shortest mutual distance in position coordinates between different scan chain groups are decided upon as flip-flop candidates for connecting scan chains, and the sequence for connecting scan chain groups is in order of decreasing mutual distance between flip-flop candidates for connecting scan chains.
[Patent Document 1] Japanese Patent Kohyo Publication No. JP-P2003-513286A
[Patent Document 2] Japanese Patent Kokai Publication No. JP-P2005-223171A
Patent Document 1 discloses a test circuit and test method which, when a scan path test is conducted, are for individually controlling a plurality of clock domains having different test clock rates and testing the plurality of clock domains simultaneously. In the system according to Patent Document 1, each of a plurality of clock domains having different test clock rates can be tested, and the plurality of clock domains can be tested simultaneously. However, with regard to the state of internal logic that has been stored in the scannable memory elements (scanned flip-flops), the result of compression by an MISR (result compression circuit) in a BIST controller is observed from an external terminal in the scan-out interval (i.e., in the scan shift operation). Consequently, it is very difficult to specify fault location in a case where the fault exists in the internal logic. Furthermore, since the result is compressed and output by the MISR, a circuit configuration in which the state of the internal logic is indeterminate is not allowed. Accordingly, a problem which arises is that it is necessary to add on a test circuit for the purpose of avoiding undefined circumstances.
Further, in the system according to Patent Document 1, a BIST function is used as an arrangement that controls a plurality of clock domains having different test clock rates. As a result, it is necessary to add on large-scale circuitry such as an auxiliary controller and BIST controller. This invites a major increase in the circuit area of a small-scale semiconductor integrated circuit. It is difficult, therefore, to actually employ Patent Document 1.
The system of Patent Document 2, on the other hand, illustrates a method of preventing wiring congestion when all scan chains are configured by connecting groups in a semiconductor integrated circuit in which a plurality of scan chain groups have been configured. In order to deal with a limitation in the number of scan chains that can be implemented in a semiconductor integrated circuit, this is a technique that reduces the wiring congestion of all scan chains by constructing a scan chain for every individual clock group system and then taking the physical positional relationship of flip-flops, etc., in the layout into consideration when deciding the sequence for connecting clock groups in which the scan chains have been constructed. However, the number of scan path test clock terminals separately required in a case where a scan path test is conducted cannot be reduced.
This causes an increase in the number of terminals of the semiconductor integrated circuit. Problems which arise are an increase in the chip cost of the semiconductor integrated circuit; an increase in the area of the mounting chip occupied, which is attendant upon an increase in package size; and a decline in test efficiency and an increase in test cost owing to a limitation in quantity at the time of parallel testing for testing a plurality of circuits simultaneously by an LSI tester.